PCB Trace Width & Ampacity Calculator
Enter current or width, copper weight and temperature rise to size a PCB trace with resistance, voltage drop and fusing estimate.
Step-by-step
- Enter valid values to begin.
This tool uses the IPC-2221 equation I = k·ΔT0.44·A0.725 (A in mil²), derived from the old IPC-2221 chart (about 0.5–3 oz, ΔT 10–100 °C, up to roughly 35 A). IPC-2152 supersedes the chart: it shows IPC-2221 is conservative for external traces and that board thickness, copper planes, nearby heat sources and airflow change the result, so use IPC-2152 data or thermal testing for borderline designs. Resistance uses ρ = 1.72 × 10−8 Ω·m at 20 °C with 0.00393/°C at the operating temperature. Fusing current is the adiabatic Onderdonk estimate and only a rough upper bound for a trace on laminate.
PCB Trace Width: Heat, Not Voltage, Sets the Limit
Core Engineering Principles
A trace carries current until its own heating outruns the board’s ability to shed heat, and the number we design to is the temperature rise ΔT above ambient. IPC-2221 expresses the old chart as I = k·ΔT0.44·A0.725, with A in mil² and k = 0.048 for outer layers, 0.024 for inner ones. The exponent 0.725 is the lesson: double the copper area and current only grows by about 65%, because wider traces shed heat less efficiently per unit area. An internal trace has half the k, and 21/0.725 is 2.6, so the same current needs about 2.6 times the area. Our 3 A example needs 54 mil outside but 140 mil inside.
Treat the result as a starting point. IPC-2152 replaced the chart after real measurements and found IPC-2221 conservative for external traces, while showing that board thickness, copper planes, nearby heat sources and airflow shift the answer by large margins. Also remember copper resistance climbs 0.393% per °C, so voltage drop and power loss at the operating temperature exceed the cold figures. Fusing is a different regime: the Onderdonk equation is adiabatic and gives a theoretical melting current, but laminate chars well before copper melts.
R = ρ(T)·L / A, ρ(T) = 1.72×10−8[1 + 0.00393(T−20)] • Ifuse = Acmil√(log10(1+(Tm−Ta)/(234+Ta)) / 33t)
NEC & Standard References
IPC-2221 (Generic Standard on Printed Board Design) is the source of the equation, and IPC-2152 (Standard for Determining Current-Carrying Capacity in Printed Board Design) supersedes its chart; this tool uses the 2221 form. IPC-6012 sets finished copper and plating requirements for rigid boards, and UL 796 sets the maximum operating temperature of the laminate. Voltage spacing between conductors comes from the IPC-2221 spacing rules and the safety standard for your product. Confirm the edition your fab and customer call out.1. ΔT0.44 = 100.44 = 2.754, so k·ΔT0.44 = 0.1322.
2. A = (3 / 0.1322)1.3793 = 74.2 mil².
3. Width = 74.2 / 1.378 = 53.8 mil = 1.37 mm. The internal equivalent is 140 mil (3.56 mm).
4. At 35 °C, ρ = 1.821×10−8 Ω·m, giving 380.7 mΩ/m and 19.0 mΩ over 50 mm.
5. Drop = 3 × 0.019 = 57 mV; loss = 171 mW.
6. Onderdonk fusing at 1 s ≈ 13.8 A, an upper bound, not a design value.
- Neck-downs set the limit. A trace that narrows at a pad or via is only as good as its narrowest section; widen it or add parallel vias.
- Vias carry less than you think. A single small via is a poor path for several amps; use several and check plating thickness.
- Thickness varies. Finished outer copper is often thicker than nominal after plating, but inner layers are not, so don’t borrow numbers across layers.
- Don’t design to the fusing current. Laminate and solder fail first; this value is a ceiling for fault analysis.