Microstrip Impedance Calculator
Enter trace geometry and substrate to get microstrip impedance, delay and wavelength, or solve for the 50 Ω width.
Step-by-step
- Enter valid values to begin.
Surface microstrip with a ground plane, air above, no solder mask. Uses the Hammerstad–Jensen/Wheeler closed forms in IPC-2141 style: finite-thickness width correction, quasi-static εeff and Z0. Accuracy is roughly ±2–5% (best for 0.1 < W/H < 10); solder mask, etch trapezoid, dispersion and glass-weave effects are ignored. FR-4 εr varies with frequency and resin content, so for production use your fab’s field-solver stackup and impedance coupons.
Microstrip Impedance: Getting 50 Ω Out of a Copper Strip
Core Engineering Principles
A microstrip is a trace over a ground plane, with the dielectric underneath and air above. The field lives partly in each, so the wave sees an effective permittivity between 1 and εr, about 3.33 for a wide trace on FR-4 at εr = 4.4. Impedance is roughly √(L/C): widen the trace and you add capacitance and drop Z0; thicken the dielectric and you lose capacitance and raise it. That is why 50 Ω lands near 3 mm on 1.6 mm FR-4 and near 0.35 mm on a thin 0.2 mm prepreg. The same εeff sets the speed, c/√εeff or about 55% of light, which is 6.1 ps per millimetre of delay.
The closed-form equations are good to a few percent, and no better. They ignore the solder mask, which typically pulls Z0 down by a few ohms. They ignore the trapezoidal etch profile, the glass-weave skew that makes one trace on a bundle faster than its neighbour, and the way εr slides with frequency and resin content. Use this tool to pick a starting width and to understand the trends, then hand the fab your target impedance and tolerance and let them size the trace to their own stackup with a field solver. They will confirm with TDR coupons.
Z0 = 60/√εeff·ln(8H/W + W/4H) (W/H ≤ 1) • 120π / (√εeff(W/H + 1.393 + 0.667 ln(W/H + 1.444))) (W/H ≥ 1)
NEC & Standard References
IPC-2141 (Design Guide for High-Speed Controlled Impedance Circuit Boards) gives the microstrip design equations and the effect of geometry on impedance. The closed forms follow the work of Hammerstad and Jensen. IPC-TM-650 contains the TDR test methods used to verify impedance coupons, and IPC-2221 covers general layout. Laminate suppliers publish the εr versus frequency curve for their materials; use that instead of the preset when it exists.1. W/H = 1.875; ΔW = (T/π)(1 + ln(2H/T)) = 61.5 µm, so Weff = 3.061 mm.
2. εeff = 2.7 + 1.7 / √(1 + 12/1.913) = 3.330.
3. Z0 = 377 / (√3.330 × 2.988) = 50.2 Ω.
4. Velocity = 1.643×108 m/s, a delay of 6.09 ps/mm (154.6 ps/inch).
5. At 1 GHz, λg = 164.3 mm and the quarter-wave length is 41.1 mm.
6. The solver returns a width of 3.02 mm for exactly 50.0 Ω.
- Specify the stackup, not just the width. A trace that’s 50 Ω on one prepreg thickness is 60 Ω on another.
- Reference plane gaps ruin it. Crossing a split in the plane breaks the return path and the impedance with it.
- Solder mask lowers Z0. If your coupon reads low by a few ohms, that’s why.
- Thickness correction is approximate. It gets weaker when T/H passes about 0.1, as with heavy copper.
- FR-4 loses signal at GHz. Dielectric and conductor loss grow with frequency; impedance alone doesn’t guarantee a clean link.